MC145170 PLL Anyone?


From: W. Daniel, 9V1ZV (
Date: Tue Apr 09 1996 - 23:54:14 EDT

Hi Gang,

        To follow up on the suggested PLL VFO, I've checked up on some
prospective parts. In particular there is this Motorola MC145170 which looks
really good to me (but I am not that experienced with PLL) so I thought
maybe I'd find out what some of the experts here think.

        One of the major problems with PLL's is that it is difficult to achieve
the small tuning steps necessary for HF amateur operation. This is typically
100 Hz, maybe less on some high end equipment. But I think 100 Hz is quite
sufficient where I come from. The PLL frequency can be represented by the
following formula:-

        fO = N * fREF * P

where fO is the output frequency, N is the programmable divider, fREF is the
reference oscillator frequency and P is the external prescaling. For the
case where no external prescaler is used (is this possible), P = 1 so the
equation now becomes:-

        fO = N * fREF

        From the above equation, we can see that the channel spacing is
constrained by fREF. Thus for a tuning step of 100 Hz, fREF needs to be a
very accurate 100 Hz. Now, if fO is to be say 5 MHz, you will find that N
works out to be 50,000. Unfortunately most PLL's are built with 14-bit
dividers yielding a division of only 16,000+ which is insufficient. Looking
at the data book, I found that the MC145170 in fact has a 16-bit divider
which gives us a division in the range of 40 to 65535. What this means is
that with a 100 Hz fREF, we can use the part, without external prescaling,
to generate frequencies from 4 kHz to 6.5 MHz in steps of 100 Hz. Of course,
this is not possible in practice because the VCO limits the range of
frequencies possible. What it does mean, as far as I can tell, is that it
should not be difficult to implement a PLL controlled VFO for a frequency
that falls anywhere in that region, while retaining a tuning step of 100 Hz.

        Now as for the fREF, the part actually has a programmable prescaler for
the fREF with a 15-bit divider. This means you can take almost any suitable
crystal filter and have it divided internally to the required 100 Hz
reference frequency. This helps out on the stability question. I suppose if
the VFO frequency is below about 3 MHz, you can achieve 50 Hz tuning steps
even with the said part. Typical current peaks for this 16-pin part is about
1.6 mA with quiescent currents of about 100 uA.

        For VFO frequencies higher than about 6 MHz, I think one will have to
resort to:-

        1. DDS
        2. Dual-modulus prescaling PLL's
        3. Dual PLL loops
        4. Mix down, etc.

All are somewhat more complicated than with the above mentioned MC145170

        So, is my analysis correct? Comments from more experienced designers? Am
I on the right track? Did I overlook anything important?

73 de 9V1ZV Daniel

 Daniel Wee |
 9V1ZV      |

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